Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography

Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. xmlns:xlink="http://www.w3.org/1999/xlink">Binary Ring -LWE (BRLWE) new optimized variant RLWE, which achieves smaller complexity higher hardware implementations. In this paper, two architectures based on xmlns:xlink="http://www.w3.org/1999/xlink">Linear-Feedback Shift Register (LFSR) arithmetic used in xmlns:xlink="http://www.w3.org/1999/xlink">Inverted Binary ( xmlns:xlink="http://www.w3.org/1999/xlink">Inv BRLWE)-based are presented, namely operation $A\cdot B+C$ over polynomial ring notation="LaTeX">$\mathbb {Z}_{q}/(x^{n}+1)$ . The first architecture optimizes resource usage major computation has novel input processing setup speed up overall latency with minimized loading cycles. second deploys an innovative serial-in serial-out format reduce involved area further yet maintains regular time-complexity. Experimental results show presented here improve complexities obtained by competing schemes found literature, e.g., involving 71.23% less area-delay product than recent designs. Both highly terms area-time can be extended deploying different lightweight application environments.